ADCMPINTEN3=DISABLED, ADCMPINTEN9=DISABLED, ADCMPINTEN7=DISABLED, ADCMPINTEN2=DISABLED, ADCMPINTEN8=DISABLED, OVR_INTEN=DISABLED, ADCMPINTEN4=DISABLED, SEQA_INTEN=DISABLED, ADCMPINTEN10=DISABLED, ADCMPINTEN5=DISABLED, ADCMPINTEN0=DISABLED, SEQB_INTEN=DISABLED, ADCMPINTEN1=DISABLED, ADCMPINTEN11=DISABLED, ADCMPINTEN6=DISABLED
A/D Interrupt Enable Register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated.
| SEQA_INTEN | Sequence A interrupt enable. 0 (DISABLED): Disabled. The sequence A interrupt/DMA request is disabled. 1 (ENABLED): Enabled. The sequence A interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. |
| SEQB_INTEN | Sequence B interrupt enable. 0 (DISABLED): Disabled. The sequence B interrupt/DMA request is disabled. 1 (ENABLED): Enabled. The sequence B interrupt/DMA request is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. |
| OVR_INTEN | Overrun interrupt enable. 0 (DISABLED): Disabled. The overrun interrupt is disabled. 1 (ENABLED): Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt request. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt request to be asserted. |
| ADCMPINTEN0 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN1 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved. |
| ADCMPINTEN2 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN3 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN4 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN5 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN6 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved. |
| ADCMPINTEN7 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN8 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN9 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN10 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| ADCMPINTEN11 | Threshold comparison interrupt enable. 0 (DISABLED): Disabled. 1 (OUTSIDE_THRESHOLD): Outside threshold. 2 (CROSSING_THRESHOLD): Crossing threshold. 3 (RESERVED): Reserved |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |